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DS18B20-PAR
 
8 of 19 
HARDWARE CONFIGURATION Figure 9 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
TRANSACTION SEQUENCE
The transaction sequence for accessing the DS18B20-PAR is as follows:
Step 1. Initialization
Step 2. ROM Command (followed by any required data exchange)
Step 3. DS18B20-PAR Function Command (followed by any required data exchange)
It is very important to follow this sequence every time the DS18B20-PAR is accessed, as the DS18B20-
PAR will not respond if any steps in the sequence are missing or out of order. Exceptions to this rule are
the Search ROM [F0h] and Alarm Search [ECh] commands. After issuing either of these ROM
commands, the master must return to Step 1 in the sequence.
 
INITIALIZATION
All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence
consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the
slave(s). The presence pulse lets the bus master know that slave devices (such as the DS18B20-PAR) are
on the bus and are ready to operate. Timing for the reset and presence pulses is detailed in the
1-WIRE SIGNALING section.
 
ROM COMMANDS
After the bus master has detected a presence pulse, it can issue a ROM command. These commands
operate on the unique 64bit ROM codes of each slave device and allow the master to single out a
specific device if many are present on the 1-Wire bus. These commands also allow the master to
determine how many and what types of devices are present on the bus or if any device has experienced an
alarm condition. There are five ROM commands, and each command is 8 bits long. The master device
must issue an appropriate ROM command before issuing a DS18B20-PAR function command. A
flowchart for operation of the ROM commands is shown in Figure 10.
SEARCH ROM [F0h]
When a system is initially powered up, the master must identify the ROM codes of all slave devices on
the bus, which allows the master to determine the number of slaves and their device types. The master
learns the ROM codes through a process of elimination that requires the master to perform a Search ROM
V
PU
 
4.7K
5 糀
Typ.
R  
T  
DS18B20-PAR 1-WIRE PORT
100 ?/SPAN>
M   FET
T
X
R
R
X
 = RECEIVE
T = TRANSMIT 
1-wire bus
DQ
Pin
V
PU
 
Micro-
processor
Strong
Pullup
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